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ds07-16505-2e fujitsu semiconductor data sheet proprietary 32-bit microcontroller cmos fr60 mb91310 series MB91F312A/fv310a n description the fr families are lines of single-chip microcontrollers based on a 32-bit high-performance risc cpu, incor- porating a variety of i/o resources for embedded control applications which require high cpu performance for high-speed processing. the fr families are best suited for embedded applications which require high-performance cpu power for processing, such as tv and pop control. based on the fr30/fr40 family cpu, this fr60 family is enhanced in bus access for use in faster applications. n feature fr cpu ? 32-bit risc, load/store architecture with a five-stage pipeline ? operating frequency: 40 mhz (using pll at an oscillation frequency of 10 mhz) ? 16 - bit fixed length instructions (basic instructions), 1 instruction per cycle ? instruction set optimized for embedded applications: memory-to-memory transfer, bit manipulation, barrel shift etc. (continued) n pac k ag e 144-pin plastic lqfp (ftp-144p-m08) 4 .com u datasheet
mb91310 series 2 ? instructions adapted for high-level languages: function entry/exit instructions, multiple-register load/store in- structions ? register interlock functions: facilitating coding in assemblers ? on-chip multiplier supported at the instruction level. signed 32-bit multiplication: 5 cycles. signed 16-bit multiplication: 3 cycles ? interrupt (pc, ps save): 6 cycles, 16 priority levels ? harvard architecture allowing program access and data access to be executed simultaneously ? instruction prefetch function implemented by a four-word queue in the cpu ? instruction compatible with fr family bus interface this bus interface is used for macro connection. (usb, ms-if, osdc) ? operating frequency max 20 mhz ? 16-bit data input/output (interface to the usb, ms-if, and osdc) ? chip-select signals can be output for completely independent eight areas allocatable in a minimum of 64 kb. the cs1 , cs2 , and cs3 areas are reserved as follows. cs0 , cs4 , to cs3 are mnusable. cs1 area : usb host cs2 area : usb function cs3 area : ms-if, osdc ? basic bus cycle : 2 cycles ? programmable automatic wait cycle generator capable of inserting wait cycles for each area cs1 , cs2 and cs3 are reserved; their settings are fixed. built-in ram ? 16 kb built ram capacity ? this ram can be used as instruction ram by writing instruction code as well as data. dmac (dma controller) ? connected to five channels (ch0, ch1 ? usb function; ch2 ? ms-if). ? 3 forwarding factors (internal peripheral/software) ? addressing using 32 - bit full addressing mode (increment, decrement, fixed) ? demand transfer, burst transfer, step transfer, or block transfer ? selectable transfer data size: 8-bit, 16-bit, or 32-bit bit search module (for realos) ? search for the position of the bit 1/0-changed first in one word from the msb reload timer (including 1 channel for realos) ? 16-bit ppg timer ch3 ? the internal clock is optional from 2/8/32 en surroundings. (continued) 4 .com u datasheet
mb91310 series 3 uart ? full duplex double buffer ? uart : 5 channels ? with parity / no parity selection ? asynchronous (start - stop synchronized) or clk - synchronous communications selectable ? internal timer for dedicated baud rate ? external clock can be used as transfer clock ? assorted error detection functions (for parity, frame, and overrun errors) i 2 c interface interrupt controller ? a total of five external interrupt lines are provided (1 nonmaskable interrupt pin (nmi ) and 4 normal interrupt pins (int3 to int0). ? interrupt from internal peripheral devices. ? programmable priorities (16 levels) for all interrupts except the non - maskable interrupt ? available for wakeup from stop mode a/d converter ? 10-bit resolution. 10 channels ? successive comparator type, conversion time : approx. 10 m s ? conversion modes (single conversion mode, scan conversion mode) ? startup sources (software and external triggers) ppg ? 4 channels ? six-bit down-counter, 16-bit data register with cycle setting buffer ? the internal clock is optional from 1/4/16/64 en surroundings. pwc ? one channel (input) incorporated ? 16 bits up counter ? simple lfp digital filter incorporated timer ? lowpass filter eliminating noise below the clock setting ? capable of pulse width measurement according to fine settings using seven types of clock signals ? event count function based on pin input ? interval timer function using seven different clocks and one external input clock (continued) ? four channels are incorporated. (ch3 can be used as two ports.) ? master/slave sending and receiving ? arbitration function ? clock synchronization function ? slave address and general call address detection function ? detecting transmitting direction function ? start condition repeat generation and detection function ? bus error detection function ? 10 bit/7 bit slave address ? standard mode (max 100 kbps)/high speed mode (max 400 kbps) supported 4 .com u datasheet
mb91310 series 4 (continued) usb host function ? u.s.b 1.0 specification ? 8 kb of internal ram for parameters usb function ? usb 1.1 compliant full-speed double buffering ? control in/out, bulk in/out, interrupt in osdc function ? high-quality osdc integrated ? analog rgb interface (with internal dac) ? digital rgb i/f ? internal dot clock generator pll other internal times ? 16-bit ppg timer ch3(u-timer) ? watch dog timer i/o port ? max 72 ports other features ? internal oscillator circuit as clock source ?init is prepared as a reset terminal. ? watchdog timer reset. software reset. ? low power consumption modes supported: stop mode and sleep mode ? gear function ? built-in time base timer ? package : lqfp-144, 0.5 mm pitch, 20 mm 20 mm ? cmos technology (0.25 m m) ? supply voltage: dual power supplies at 3.3 v 0.3 v, 2.5 v 0.2 v the i 2 c license : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. 4 .com u datasheet
mb91310 series 5 n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 docki fh vsync hsync vgs cpo vss vddi (pll) vddr (2.5 v) vref (1.1 v) vro (2.7 k w ) rcomp (0.1 m f) rout vssr vddg (2.5 v) gcomp (0.1 m f) gout vssg vddb (2.5 v) bcomp (0.1 m f) bout vssb avcc avrh avss/avrl an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 p00/scl0 ibreak iclk trst vss vddi vdde nmi p65/int3 p64/int2 p63/int1 p62/int0 p61 p60/atrg p57/trg3 p56/trg2 p55/trg1 p54/trg0 p53/tmi3 p52/tmi2 p51/tmi1 p50/tmi0 md3 md2 md1 md0 p47/ppg3 p46/ppg2 p45/ppg1 p44/ppg0 x1a vss x0a vddi vdde p43/tmo3 p42/tmo2 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p01/sda0 p02/scl1 p03/sda1 vdde vddi(pll) x0 vss x1 init p04/scl2 p05/sda2 p06/scl3 p07/scl4 p10/sda3 p11/sda4 p12/si0 p13/so0 p14/sck0 p15/si1 p16/so1 p17/sck1 p20/si2 p21/so2 p22/sck2 p23/si3 p24/so3 p25/sck3 p30/si4/tin0 p31/so4/tin1 p32/sck4/tin2 p33/to0 p34/to1 p35/to2 p36/rin p40/tmo0 p41/tmo1 dcko vob1 vob2 vdde vddi vss r2 r1 r0 g2 g1 g0 b2 b1 b0 uhp uhm udp udm vdde vddi x1b vss x0b p74 p73 p72 p71 p70 icd3 icd2 icd1 icd0 ics2 ics1 ics0 (top view) 4 .com u datasheet
mb91310 series 6 n pin description (continued) pin no. pin name circuit type description 1 docki d dot clock input 2 fh d vertical synchronous output 3 vsync d horizontal synchronous input 4 hsync d vertical synchronous input 5vgs ? device ground 6 cpo k charge pump output 7 vss ? dot clock pll ground 8vddi (pll) ? dot clock pll power supply 9 vddr (2.5 v) ? d/a power supply for r 10 vref (1.1 v) k voltage reference input 11 vro (2.7 k w ) k resistor connection pin 12 rcomp (0.1 m f) k capacitor connection pin 13 rout k r output (analog) 14 vssr ? d/a ground for r 15 vddg (2.5 v) ? d/a power supply for g 16 gcomp (0.1 m f) k capacitor connection pin 17 gout k g output (analog) 18 vssg ? device ground for g 19 vddb (2.5 v) ? d/a power supply for b 20 bcomp (0.1 m f) k capacitor connection pin 21 bout k b output (analog) 22 vssb ? d/a ground for b 23 avcc ? a/d power supply 24 avrh ? a/d referense power supply 25 avss/avrl ? a/d ground 26 an0 e analog input 27 an1 e analog input 28 an2 e analog input 29 an3 e analog input 30 an4 e analog input 31 an5 e analog input 32 an6 e analog input 33 an7 e analog input 34 an8 e analog input 35 an9 e analog input 4 .com u datasheet
mb91310 series 7 (continued) pin no. pin name circuit type description 36 p00 c general-purpose port scl0 i 2 c clock pin 37 p01 c general-purpose port sda0 i 2 c data pin 38 p02 c general-purpose port scl1 i 2 c clock 39 p03 c general-purpose port sda1 i 2 c data pin 40 vdde ? 3.3 v power supply 41 vddi (pll) ? 2.5 v power supply 42 x0 a 10-mhz oscillation pin 43 vss ? ground 44 x1 a 10-mhz oscillation pin 45 init b initial (reset) pin 46 p04 c general-purpose port scl2 i 2 c clock 47 p05 c general-purpose port sda2 i 2 c data pin 48 p06 n general-purpose port scl3 i 2 c clock 49 p07 general-purpose pors scl4 i 2 c clock 50 p10 n general-purpose port sda3 i 2 c data pin 51 p11 general-purpose port sda4 i 2 c data pin 52 p12 c general-purpose port si0 uart0 serial input 53 p13 c general-purpose port so0 uart0 serial output 54 p14 c general-purpose port sck0 uart0 clock input/output 55 p15 c general-purpose port si1 uart1 serial input 56 p16 c general-purpose port so1 uart1 serial output 4 .com u datasheet
mb91310 series 8 (continued) pin no. pin name circuit type description 57 p17 c general-purpose port sck1 uart1 clock input/output 58 p20 c general-purpose port si2 uart2 serial input 59 p21 c general-purpose port so2 uart2 serial output 60 p22 c general-purpose port sck2 uart2 clock input/output 61 p23 c general-purpose port si3 uart3 serial input 62 p24 c general-purpose port so3 uart3 serial output 63 p25 c general-purpose port sck3 uart3 clock input/output 64 p30 c general-purpose port si4 uart4 serial input tin0 reload timer 0 trigger input 65 p31 c general-purpose port so4 uart4 serial output tin1 reload timer 1 trigger input 66 p32 c general-purpose port sck4 uart4 clock input/output tin2 reload timer 2 trigger input 67 p33 c general-purpose port to0 reload timer 0 output 68 p34 c general-purpose port to1 reload timer 1 output 69 p35 c general-purpose port to2 reload timer 2 output 70 p36 c general-purpose port rin pwc input 71 p40 c general-purpose port tmo0 multi-function timer 0 output 72 p41 c general-purpose port tmo1 multi-function timer 1 output 4 .com u datasheet
mb91310 series 9 (continued) pin no. pin name circuit type description 73 p42 c general-purpose port tmo2 multi-function timer 2 output 74 p43 c general-purpose port tmo3 multi-function timer 3 output 75 vdde ? 3.3 v power supply 76 vddi ? 2.5 v power supply 77 x0a a 32 khz oscillation pin 78 vss ? ground 79 x1a a 32 khz oscillation pin 80 p44 c general-purpose port ppg0 ppg0 output 81 p45 c general-purpose port ppg1 ppg1 output 82 p46 c general-purpose port ppg2 ppg2 output 83 p47 c general-purpose port ppg3 ppg3 output 84 md0 f mode pins 85 md1 f mode pins 86 md2 f mode pins 87 md3 f mode pins (ground) 88 p50 c general-purpose port tmi0 multi-function timer 0 input 89 p51 c general-purpose port tmi1 multi-function timer 1 input 90 p52 c general-purpose port tmi2 multi-function timer 2 input 91 p53 c general-purpose port tmi3 multi-function timer 3 input 92 p54 ? general-purpose port trg0 ppg0 trigger input 93 p55 ? general-purpose port trg1 ppg1 trigger input 94 p56 ? general-purpose port trg2 ppg2 trigger input 4 .com u datasheet
mb91310 series 10 (continued) pin no. pin name circuit type description 95 p57 c general-purpose port trg3 ppg3 trigger input 96 p60 c general-purpose port atrg a/d conversion trigger input 97 p61 c general-purpose port 98 p62 o general-purpose port int0 external interrupt input 0 99 p63 o general-purpose port int1 external interrupt input 1 100 p64 o general-purpose port int2 external interrupt input 2 101 p65 o general-purpose port int3 external interrupt input 3 102 nmi bnmi input 103 vdde ? 3.3 v power supply 104 vddi ? 2.5 v power supply 105 vss ? ground 106 trst b dsu tool reset 107 iclk c dsu clock 108 ibreak l dsu break 109 ics0 m dsu status 110 ics1 m dsu status 111 ics2 m dsu status 112 icd0 h dsu data 113 icd1 h dsu data 114 icd2 h dsu data 115 icd3 h dsu data 116 p70 i general-purpose port 117 p71 c general-purpose port 118 p72 c general-purpose port 119 p73 c general-purpose port 120 p74 h general-purpose port 121 x0b a 48 mhz oscillation pin 122 vss ? ground 4 .com u datasheet
mb91310 series 11 (continued) pin no. pin name circuit type description 123 x1b a 48 mhz oscillation pin 124 vddi ? 2.5 v power supply 125 vdde ? 3.3 v power supply 126 udm usb usb-function 127 udp usb-function 128 uhm usb usb-host 129 uhp usb-host 130 b0 d rgb digital output 131 b1 d rgb digital output 132 b2 d rgb digital output 133 g0 d rgb digital output 134 g1 d rgb digital output 135 g2 d rgb digital output 136 r0 d rgb digital output 137 r1 d rgb digital output 138 r2 d rgb digital output 139 vss ? ground 140 vddi ? 2.5 v power supply 141 vdde ? 3.3 v power supply 142 vob2 d semi transparent color periodoutput 143 vob1 d osd display period output 144 dcko d dot clock output 4 .com u datasheet
mb91310 series 12 n i/o circuit type (continued) type circuit type remarks a ? oscillation circuit b ? cmos hysteresis input with pull-up resistance c ?cmos level output. cmos level hysteresis input with standby control d ? 2.5 v cmos level output. cmos level hysteresis input with standby control x1 standby control x0 clock input digital input standby control digital output digital output digital input 2.5 v standby control digital input digital output digital output 4 .com u datasheet
mb91310 series 13 (continued) type circuit type remarks e ? analog input with switch f ? cmos level input without standby control g ? cmos level hysteresis input without standby control h ? cmos level output hysteresis input standby control provided pull-down resistor provided input control analog input digital input digital input standby control digital output digital output digital input 4 .com u datasheet
mb91310 series 14 (continued) type circuit type remarks i ? cmos level output hysteresis input standby control provided pull-up resistor provided j ? open drain output cmos level hysteresis input with standby control k ? analog pin l ? cmos hysteresis input with pull-down resistance standby control digital output digital output digital input standby control open drain control digital output digital input digital input 4 .com u datasheet
mb91310 series 15 (continued) type circuit type remarks m ? cmos level output n ? two ports for i 2 c cmos hysteresis input cmos output stop control provided o ? cmos level output cmos hysteresis input open drain control digital output input control open drain control digital output digital input digital input digital output open drain control digital output digital output digital input 4 .com u datasheet
mb91310 series 16 n handling devices preventing latchup latch-up may occur in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if an above-rating voltage is applied between v cc and v ss . a latchup,if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. when you use a cmos ic, be very careful not to exceed the maximum rating. treatment of unused input pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull- up or pull-down resistor. about power supply pins if there are multiple vcc and vss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the vcc and vss pins to the power supply and ground externally. the power pins should be connected to v cc and v ss of this device at the lowest possible impedance from the current supply source. it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 m f between vcc and vss near this device. about crystal oscillator circuit noise near the x0 and x1 pin may cause the device to malfunction. when designing a pc board using the device, place the x0 and x1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible. it is strongly recommended to design pc board so that x0 and x1 pins are surrounded by grounding area for stable operation. about mode pins (md0 to md3) these pins should be connected directly to vcc or vss. to prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and vcc or v.0 is as short as possible and the connection impedance is low. about tool reset pin (trst ) this pin must input the same signal as that to init when the tool is not used. apply the same treatment to mass- produced products as well. operation at start-up a setting initialization reset (init) must always be performed via the init pin immediately after the power supply is turned on or recycled. immediately after the power supply is turned on, hold the low level input to the init pin for the settling time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (for init via the init pin, the oscillation stabilization wait time setting is initialized to the minimum value.) 4 .com u datasheet
mb91310 series 17 oscillation input at power-on when turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. notes on power-on/shut-down cautions to take when turning on/off vddi (2.5-v internal power supply) and vdde (3.3-v external-pin power supply) do not apply vdde (external) alone continuously (for over an indication of one minute) with vddi (internal) disconnected not to cause a reliability problem with the lsi. when vdde (external) returns from the off state to the on state, the circuit may fail to hold its internal state, for example, due to power supply noise. undefined output on power-on when the power supply is turned on, the output pin may remain indeterminate until the internal power supply becomes stable. about the attention when the external clock is used when the external clock is used, in principle, supply a clock signal to the x0 (x0a, x0b) pin and an opposite- phase clock signal to the x1 (x1a, x1b) pin at the same time. however, in this case. the stop mode must not be used.(this is because, in stop mode, the x1 (x1a, x1b) pin stops at h output.) at 12.5 mhz or less, the device can be used with the clock signal supplied only to the x0 (x0a, x0b) pin. an example of using the external clock is illustrated below. note : the x1 (x1a, x1b) pin must be designed to have a delay within 15 ns, at 10 mhz, from the signal to the x0 (x0a, x0b) pin. when the power is turned on vddi (internal) ? analog ? vdde (external) ? signal when the power is turned off signal ? vdde (external) ? analog ? vddi (internal) x0, x0a, x0b x1, x1a, x1b MB91F312A/fv310a [stop mode (oscillation stop mode) cannot be used.] external clock usage (normal) x0, x1a, x1b x1, x1a, x1b MB91F312A/fv310a open external clock usage (enabled at 12.5 mhz max.) 4 .com u datasheet
mb91310 series 18 restrictions common in the mb91310 series (1) clock control block take the oscillation stabilization wait time during low level input to the init pin. (2) bit search module the 0-detection data register (bsd0), 1-detection data register (bsd1), and transition-detection data register (bsdc) are only word-accessible. (3) i/o port ports are accessed only in bytes. (4) low power consumption mode to enter the standby mode, use the synchronous standby mode (set with the syncs bit as bit 8 in the tbcr, or time-base counter control register) and be sure to use the following sequence: in addition, set the i-flag and the ilm and icr registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode. please do not do the following when the monitor debugger is used. ? set a break point within the above array of instructions. ? single-step the above instructions. (5) pre-fetch when accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only. byte or half-word access results in wrong data read. (6) notes on the ps register as the ps register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the ps register to be updated. as the microcontroller is designed to carry out reprocessing correctly upon returning from such an eit event, it performs operations before and after the eit as specified in either case. 1. the following operations are performed when (c) the instruction followed by a data event or a divou/divos emulator menu instruction (a) receives a user interrupt or nmi or (b) breaks when single-stepped. (ldi #value_of_standby, r0) (ldi #_stcr, r12) stb r0, @r12 : write to standby control register (stcr) ldub @r12, r0 : stcr lead for synchronous standby ldub @r12, r0 : dummy re-lead of stcr nop : nop 5 for timing adjustment nop nop nop nop 4 .com u datasheet
mb91310 series 19 ? the d0 and d1 flags are updated in advance. ? an eit handling routine (user interrupt, nmi, or emulator) is executed. ? upon returning from the eit, the divou/divos instruction is executed and the d0 and d1 flags are updated to the same values as in (1). 2. the following operations are performed when the orccr/stilm/mov ri and ps instructions are executed. ? the ps register is updated in advance. ? an eit handling routine (user interrupt or nmi) is executed. ? upon returning from the eit, the above instructions are executed and the ps register is updated to the same value as in (1). (7) watchdog timer the watchdog timer built in this model monitors a program to check that it defers a reset within a certain period of time. the watchdog timer resets the cpu if the program runs out of controls, preventing the reset defer function from being executed. once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on watching programs until it resets the cpu. as an exception, the watchdog timer defers a reset automatically under the condition in which the cpu stops program execution.refer to the watchdog timer function description for the exceptional condition. if the system runs out of control and develops the above condition, a watchdog reset may not be generated. in that case, please reset (init) by external init terminal. (8) notes on using the a/d converter the mb91310 series contains an a/d converter. supply power to the av cc at 3.3 v. unique to the evaluation chip mb91fv310a (1) simultaneous occurrences of a software break and a user interrupt/nmi if a software break and a user interrupt/nmi occurs simultaneously, the emulator debugger may react as follows. ? the debugger stops pointing to a location other than the programmed break points. ? the halted program is not re - executed correctly. if this symptom occurs, use a hardware break in place of a hardware break. if you use the monitor debugger, do not set a break point within the relevant array of instructions. (2) single-stepping of the reti instruction if an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping reti. this will prevent the main routine and low-interrupt-level programs from being exe- cuted. do not single-step the reti instruction for avoidance purposes. when the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. (3) about an operand break do not apply a data event break to access to the area containing the address of a stack pointer. (4) sample batch file for configuration to debug a program downloaded to internal ram, be sure to execute the following batch file after executing reset. # set modr (0x7fd) = enable in memory + 16-bit external bus set mem/byte 0x7fd = 0x5 4 .com u datasheet
mb91310 series 20 n block diagram 32 16 adapter fr cpu core flash 512 kb ram 16 kb bus converter dmac 5 ch a/d 10 ch i 2 c 4 ch u-timer 5 ch uart 5 ch ppg 4 ch pwc 1 ch osdc font flash 32 32 bit search clock control interrupt controller external interrupt ports reload timer 3 ch timer 4 ch external 48 mhz i/f usb function usb host 4 .com u datasheet
mb91310 series 21 n memory space 1. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing areas the following address space areas are used as i/o areas. these areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. the size of directly addressable areas depends on the length of the data being accessed as shown below. ? byte data access : 0-0ff h ? half word data access : 0-1ff h ? word data access : 0-3ff h 2. memory map the figure below shows the memory space of the this item kind. 0008 0000 h 0000 0000 h 0000 0400 h 0001 0000 h 0003 c000 h 0005 0000 h 0004 0000 h 0005 8000 h 0006 0000 h 0007 0000 h 0007 8000 h 0018 0000 h 0020 0000 h 0010 0000 h ffff ffff h i/o i/o usb-host (reg) usb-host (ram) usb-func ms osdc flash rom1 512 kb flash rom2 512 kb single chip mode internal rom external bus mode refer to i/o map program font direct addressing area access disallowed built-in ram external area 4 .com u datasheet
mb91310 series 22 n i/o map this shows the location of the various peripheral resource registers in the memory space. [how to read the table] note:initial values of register bits are represented as follows: 1 : initial value: 1 0 : initial value: 0 x : initial value: x - : no physical register at this location address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register read/write attribute initial value after a reset register name (first-column register at address 4n; second-column register at address 4n + 2) location of left - most register (when using word access, the register in column 1 is in the msb side of the data.) 4 .com u datasheet
mb91310 series 23 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h to 00000f h ???? reserved 000010 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] --xxxxxx pdr3 [r/w] -xxxxxxx r-bus port data register 000014 h pdr4 [r/w] xxxxxxxx pdr5 [r/w] xxxxxxxx pdr6 [r/w] --xxxxxx pdr7 [r/w] ---xxxxx 000018 h ???? 00001c h ???? 000020 h adcth [r/w] xxxxxx00 adctl [r/w] 00000x00 adch [r/w] 00000000_00000000 10 bit a/d converter 000024 h adat0 [r] xxxxxx00_00000000 adat1 [r] xxxxxx00_00000000 000028 h adat2 [r] xxxxxx00_00000000 adat3 [r] xxxxxx00_00000000 00002c h adat4 [r] xxxxxx00_00000000 adat5 [r] xxxxxx00_00000000 000030 h adat6 [r] xxxxxx00_00000000 adat7 [r] xxxxxx00_00000000 000034 h adat8 [r] xxxxxx00_00000000 adat9 [r] xxxxxx00_00000000 000038 h ???? reserved 00003c h ???? 000040 h eirr [r/w] 00000000 enir [r/w] 00000000 elvr [r/w] 00000000 ext int 000044 h dicr [r/w] -------0 hrcl [r/w] 0--11111 ? dlyi/i-unit 000048 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w] ----0000 00000000 000050 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w] ----0000 00000000 000058 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r/w] ----0000 00000000 4 .com u datasheet
mb91310 series 24 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000060 h ssr [r/w] 00001-00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00--0-0- uart0 000064 h utim [r] (utimr [w]) 00000000 00000000 drcl [w] -------- utimc [r/w] 0--00001 u-timer 0 000068 h ssr [r/w] 00001-00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00--0-0- uart1 00006c h utim [r] (utimr [w]) 00000000 00000000 drcl [w] -------- utimc [r/w] 0--00001 u-timer 1 000070 h ssr [r/w] 00001-00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00--0-0- uart2 000074 h utim [r] (utimr [w]) 00000000 00000000 drcl [w] -------- utimc [r/w] 0--00001 u-timer 2 000078 h ssr [r/w] 00001-00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00--0-0- uart3 00007c h utim [r] (utimr [w]) 00000000 00000000 drcl [w] -------- utimc [r/w] 0--00001 u-timer 3 000080 h ssr [r/w] 00001-00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00--0-0- uart4 000084 h utim [r] (utimr [w]) 00000000 00000000 drcl [w] -------- utimc [r/w] 0--00001 u-timer 4 000088 h ?? reserved 00008c h ?? 000090 h pwcc [r/w] pwcc [r/w] ? pwc 000094 h pwcd [r] xxxxxxxx_xxxxxxxx ? 000098 h ?? reserved 00009c h ?? 0000a0 h ?? 0000a4 h ?? 0000a8 h ?? 0000ac h ?? 0000b0 h ???? 0000b4 h ibcr [r/w] 00000000 ibsr [r/w] 00000000 itba [r/w] ------00 00000000 i 2 c interface ch0 0000b8 h itmk [r/w] 00----11 11111111 ismk [r/w] 01111111 isba [r/w] 00000000 0000bc h ? idar [r/w] 00000000 iccr [r/w] 0-011111 idbl [r/w] -------0 0000c0 h ???? reserved 4 .com u datasheet
mb91310 series 25 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000c4 h ibcr [r/w] 00000000 ibsr [r/w] 00000000 itba [r/w] ------00 00000000 i 2 c interface ch1 0000c8 h itmk [r/w] 00----11 11111111 ismk [r/w] 01111111 isba [r/w] 00000000 0000cc h ? idar [r/w] 00000000 iccr [r/w] 0-011111 idbl [r/w] -------0 0000d0 h ???? reserved 0000d4 h ibcr [r/w] 00000000 ibsr [r/w] 00000000 itba [r/w] ------00 00000000 i 2 c interface ch2 0000d8 h itmk [r/w] 00----11 11111111 ismk [r/w] 01111111 isba [r/w] 00000000 0000dc h ? idar [r/w] 00000000 iccr [r/w] 0-011111 idbl [r/w] -------0 0000e0 h ???? reserved 0000e4 h ibcr [r/w] 00000000 ibsr [r/w] 00000000 itba [r/w] ------00 00000000 i 2 c interface ch3 0000e8 h itmk [r/w] 00----11 11111111 ismk [r/w] 01111111 isba [r/w] 00000000 0000ec h ? idar [r/w] 00000000 iccr [r/w] 0-011111 idbl [r/w] -------0 0000f0 h t0lpcr [r/w] -----000 t0ccr [r/w] 0-010000 t0tcr [r/w] 00000000 t0r [r/w] ---00000 multi-function timer 0000f4 h t0drr [r/w] xxxxxxxx xxxxxxxx t0crr [r/w] xxxxxxxx xxxxxxxx 0000f8 h t1lpcr [r/w] -----000 t1ccr [r/w] 0-000000 t1tcr [r/w] 00000000 t1r [r/w] ---00000 0000fc h t1drr [r/w] xxxxxxxx xxxxxxxx t1crr [r/w] xxxxxxxx xxxxxxxx 000100 h t2lpcr [r/w] -----000 t2ccr [r/w] 0-000000 t2tcr [r/w] 00000000 t2r [r/w] ---00000 000104 h t2drr [r/w] xxxxxxxx xxxxxxxx t2crr [r/w] xxxxxxxx xxxxxxxx 000108 h t3lpcr [r/w] -----000 t3ccr [r/w] 0-000000 t3tcr [r/w] 00000000 t3r [r/w] ---00000 00010c h t3drr [r/w] xxxxxxxx xxxxxxxx t3crr [r/w] xxxxxxxx xxxxxxxx 000110 h ???? reserved 000120 h ptmr0 [r] 11111111_11111111 pcsr0 [w] xxxxxxxx_xxxxxxxx ppg0 000124 h pdut0 [w] xxxxxxxx_xxxxxxxx pcnh0 [r/w] 00000000 pcnl0 [r/w] 00000000 4 .com u datasheet
mb91310 series 26 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000128 h ptmr1 [r] 11111111_11111111 pcsr1 [w] xxxxxxxx_xxxxxxxx ppg1 00012c h pdut1 [w] xxxxxxxx_xxxxxxxx pcnh1 [r/w] 00000000 pcnl1 [r/w] 00000000 000130 h ptmr2 [r] 11111111_11111111 pcsr2 [w] xxxxxxxx_xxxxxxxx ppg2 000134 h pdut2 [w] xxxxxxxx_xxxxxxxx pcnh2 [r/w] 00000000 pcnl2 [r/w] 00000000 000138 h ptmr3 [r] 11111111_11111111 pcsr3 [w] xxxxxxxx_xxxxxxxx ppg3 00013c h pdut3 [w] xxxxxxxx_xxxxxxxx pcnh3 [r/w] 00000000 pcnl3 [r/w] 00000000 000140 h ???? reserved 000144 h ???? 000148 h ???? 00014c h ???? 000150 h ???? 000154 h ???? 000158 h ???? 00015c h ???? 000160 h to 0001fc h ???? 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb4 [r/w] 00000000 00000000 00000000 00000000 4 .com u datasheet
mb91310 series 27 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000224 h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000228 h ? 00022c h to 00023c h ? reserved 000240 h dmacr [r/w] 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac 000244 h to 0002fc h ? ? 000300 h to 0003ec h ? 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] 00000000 ddr1 [r/w] 00000000 ddr2 [r/w] --000000 ddr3 [r/w] -0000000 r-bus port direction register 000404 h ddr4 [r/w] 00000000 ddr5 [r/w] 00000000 ddr6 [r/w] --000000 ddr7 [r/w] ---00000 000408 h ???? 00040c h ???? 000410 h pfr0 [r/w] 0--00000 pfr1 [r/w] 00000000 pfr2 [r/w] 000---00 pfr3 [r/w] 00000000 r-bus port function register 000414 h pfr4 [r/w] 0------- ??? 000418 h ???? 00041c h ???? 000420 h to 00043c h ? reserved 4 .com u datasheet
mb91310 series 28 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02 [r/w] ---11111 icr03 [r/w] ---11111 interrupt control unit 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 interrupt control unit 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34 [r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 000470 h to 00047c h ?? 000480 h rsrr [r/w] 10000000* 2 stcr [r/w] 00110011* 2 tbcr [r/w] 00xxxx00* 1 ctbr [w] xxxxxxxx clock control unit 000484 h clkr [r/w] 00000000* 1 wpr [w] xxxxxxxx divr0 [r/w] 00000011* 1 divr1 [r/w] 00000000* 1 000488 h ?? osccr [r/w] xxxxxxx0 ?? 00048c h wpcr [r/w] b 00---000 ??? clock timer 000490 h oscr [r/w] b 00---000 ??? oscillation stabilization waiting 4 .com u datasheet
mb91310 series 29 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000494 h to 0005fc h ? reserved 000600 h ???? t-unit port direction register 000604 h ???? 000608 h ???? 00060c h ???? 000610 h ???? t-unit port function register 000614 h ???? 000618 h ???? 00061c h ???? 000620 h ? 000624 h ? 000628 h to 00063f h ? reserved 000640 h asr0 [r/w] 00000000 00000000* 1 acr0 [r/w] 1111xx00 00000000* 1 t-unit 000644 h asr1 [r/w] xxxxxxxx xxxxxxxx* 1 acr1 [r/w] xxxxxxxx xxxxxxxx* 1 000648 h asr2 [r/w] xxxxxxxx xxxxxxxx* 1 acr2 [r/w] xxxxxxxx xxxxxxxx* 1 00064c h asr3 [r/w] xxxxxxxx xxxxxxxx* 1 acr3 [r/w] xxxxxxxx xxxxxxxx* 1 000650 h asr4 [r/w] xxxxxxxx xxxxxxxx* 1 acr4 [r/w] xxxxxxxx xxxxxxxx* 1 000654 h asr5 [r/w] xxxxxxxx xxxxxxxx* 1 acr5 [r/w] xxxxxxxx xxxxxxxx* 1 000658 h asr6 [r/w] xxxxxxxx xxxxxxxx* 1 acr6 [r/w] xxxxxxxx xxxxxxxx* 1 00065c h asr7 [r/w] xxxxxxxx xxxxxxxx* 1 acr7 [r/w] xxxxxxxx xxxxxxxx* 1 000660 h awr0 [r/w] 011111111 11111111* 1 awr1 [r/w] xxxxxxxx xxxxxxxx* 1 000664 h awr2 [r/w] xxxxxxxx xxxxxxxx* 1 awr3 [r/w] xxxxxxxx xxxxxxxx* 1 000668 h awr4 [r/w] xxxxxxxx xxxxxxxx* 1 awr5 [r/w] xxxxxxxx xxxxxxxx* 1 4 .com u datasheet
mb91310 series 30 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 00066c h awr6 [r/w] xxxxxxxx xxxxxxxx* 1 awr7 [r/w] xxxxxxxx xxxxxxxx* 1 t-unit 000670 h ? 000674 h ? 000678 h iowr0 [r/w] xxxxxxxx iowr1 [r/w] xxxxxxxx iowr2 [r/w] xxxxxxxx ? 00067c h ? 000680 h cser [r/w] 000000001 cher [r/w] 11111111 ? tcr [r/w] 00000000 000684 h ? 000684 h to 0007f8 h ? reserved 0007fc h ? modr [w] xxxxxxxx ?? ? 000800 h to 000afc h ? reserved 000b00 h ests0 [r/w] x0000000 ests1 [r/w] xxxxxxxx ests2 [r] 1xxxxxxx ? dsu 000b04 h ectl0 [r/w] 0x000000 ectl1 [r/w] 00000000 ectl2 [w] 000x0000 ectl3 [r/w] 00x00x11 000b08 h ecnt0 [w] xxxxxxxx ecnt1 [w] xxxxxxxx eusa [w] xxx00000 edtc [w] 0000xxxx 000b0c h ewpt [r] 00000000 00000000 ? 000b10 h edtr0 [w] xxxxxxxx xxxxxxxx edtr1 [w] xxxxxxxx xxxxxxxx 000b14 h to 000b1c h ? 000b20 h eia0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b24 h eia1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b28 h eia2 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b2c h eia3 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b30 h eia4 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 4 .com u datasheet
mb91310 series 31 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000b34 h eia5 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dsu 000b38 h eia6 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b3c h eia7 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b40 h edta [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b44 h edtm [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b48 h eoa0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b4c h eoa1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b50 h epcr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b54 h epsr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b58 h eiam0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b5c h eiam1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b60 h eoam0/eodm0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b64 h eoam1/eodm1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b68 h eod0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b6c h eod1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b70 h to 000ffc h ? reserved 001000 h dmasa0 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 4 .com u datasheet
mb91310 series 32 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 001010 h dmasa2 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx dmac 001014 h dmada2 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001028 h to 006ffc h ? reserved 007000 h flcr [r/w] 0110_x000 ? program flash i/f 007004 h flwc [r/w] 0001_0011 ? 007008 h to 00707c h ? reserved 007080 h to 0070fc h ? reserved 007100 h fncr [r/w] 0110_x000 ? font flash i/f 007104 h fnwc [r/w] 0001_0011 ? 00050000 h hr (hc revision) [r] 00000000_00000000_00000001_00010000 usb host 00050004 h hc (hc control) [r/w] 00000000_00000000_00000000_00000000 00050008 h hcs (hc command status) [r/w] 00000000_00000000_00000000_00000000 0005000c h his (hc interrupt status) [r/w] 00000000_00000000_00000000_00000000 00050010 h hie (hc interrupt enable) [r/w] 00000000_00000000_00000000_00000000 00050014 h hid (hc interrupt disable) [r/w] 00000000_00000000_00000000_00000000 4 .com u datasheet
mb91310 series 33 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 00050018 h hhcca (hc hcca) [r/w] 00000000_00000000_00000000_00000000 usb host 0005000c h hpced (hc period current ed) [r/w] 00000000_00000000_00000000_00000000 00050020 h hched (hc control head ed) [r/w] 00000000_00000000_00000000_00000000 00050024 h hcced (hc control current ed) [r/w] 00000000_00000000_00000000_00000000 00050028 h hbhed (hc bulk head ed) [r/w] 00000000_00000000_00000000_00000000 0005002c h hbced (hc bulk current ed) [r/w] 00000000_00000000_00000000_00000000 00050030 h hdh (hc done head) [r/w] 00000000_00000000_00000000_00000000 00050034 h hfi (hc fm interval) [r/w] 00000000_00000000_00101110_11011111 00050038 h hfr (hc fm remaining) [r] 00000000_00000000_00000000_00000000 0005003c h hfn (hc fm number) [r] 00000000_00000000_00000000_00000000 00050040 h hps (hc periodic start) [r/w] 00000000_00000000_00000000_00000000 00050044 h hlst (hc ls threshold) [r/w] 00000000_00000000_00000110_00101000 00050048 h hrda (hc rh descriptor a) [r/w] 00000001_00000000_00000000_00000010 0005004c h hrdb (hc rh descriptor b) [r/w] 00000000_00000000_00000000_00000000 00050050 h hrs (hc rh status) [r/w] 00000000_00000000_00000000_000000x0 00050054 h hrps1 (hc rh port status[1]) [r/w] 00000000_00000000_00000000_00000x00 00050058 h hrps2 (hc rh port status[2]) [r/w] 00000000_00000000_00000000_00000x00 0005005c h to 00057fff h ? 00058000 h to 00059fff h sram 8 kb 0005a000 h to 0005ffff h ? 4 .com u datasheet
mb91310 series 34 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 00060000 h fifo0o [r] xxxxxxxx_xxxxxxxx fifo0i [w] xxxxxxxx_xxxxxxxx usb function 00060004 h fifo1 [r] xxxxxxxx_xxxxxxxx fifo2 [w] xxxxxxxx_xxxxxxxx 00060008 h fifo3 [r] xxxxxxxx_xxxxxxxx ? 0006000c h to 0006001f h ? 00060020 h ? cont1 [r/w] xxxxx0xx_xxx00000 00060024 h cont2 [r/w] xxxxxxxx_xxx00000 cont3 [r/w] xxxxxxxx_xxx00000 00060028 h cont4 [r/w] xxxxxxxx_xxx00000 cont5 [r/w] xxxxxxxx_xxxx00xx 0006002c h cont6 [r/w] xxxxxxxx_xxxx00xx cont7 [r/w] xxxxxxxx_xxx00000 00060030 h cont8 [r/w] xxxxxxxx_xxx00000 cont9 [r/w] xxxx0000_x000000x 00060034 h cont10 [r/w] xxxxxxxx_0xxx0000 ttsize [r/w] 00010001_00010001 00060038 h trsize [r/w] 00010001_00010001 ? 0006003c h ? 00060040 h rsize0 [r] xxxxxxxx_xxxx0000 ? 00060044 h rsize1 [r] xxxxxxxx_x0000000 ? 00060048 h to 0006005f h ? 00060060 h ? st1 [r/w] xxxxxx00_00000000 00060064 h ? 00060068 h st2 [r] xxxxxxxx_xxx00000 st3 [r/w] xxxxxxxx_xxx00000 0006006c h st4 [r/w] xxxxx000_00000000 st5 [r/w] xxxx0xxx_xx00000000 4 .com u datasheet
mb91310 series 35 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 00060070 h to 0006007d h ? usb function 0006007e h reset [r/w] 00000---_-------- ? 00060080 h to 00077fff h ? reserved 00078000 h osd_vadr [r/w] xxxxxxxx_xxxxxxxx osd_cd1 [r/w] xxxxxxxx_xxxxxxxx osdc 00078004 h osd_cd2 [r/w] xxxxxxxx_xxxxxxxx osd_rcd1 [r/w] xxxxxxxx_xxxxxxxx 00078008 h osd_rcd2 [r/w] xxxxxxxx_xxxxxxxx osd_soc1 [r/w] xxxxxxxx_0000xxxx 0007800c h osd_soc2 [r/w] xxxxxxxx_xxxxxxxx osd_vdpc [r/w] xxxxxxxx_xxxxxxxx 00078010 h osd_hdpc [r/w] xxxxxxxx_xxxxxxxx osd_cvsc [r/w] xxxxxxxx_xxxxxxxx 00078014 h osd_sbfcc [r/w] xxxxxxxx_xxxxxxxx osd_thcc [r/w] xxxxxxxx_xxxxxxxx 00078018 h osd_gfcc [r/w] xxxxxxxx_xxxxxxxx osd_sbcc1 [r/w] xxxxxxxx_xxxxxxxx 0007801c h osd_sbcc2 [r/w] xxxxxxxx_xxxxxxxx osd_spcc1 [r/w] xxxxxxxx_xxxxxxxx 00078020 h osd_spcc2 [r/w] xxxxxxxx_xxxxxxxx osd_spcc3 [r/w] xxxxxxxx_xxxxxxxx 00078024 h osd_spcc4 [r/w] xxxxxxxx_xxxxxxxx osd_syncc [r/w] xxxxxxxx_xxxxxxxx 00078028 h osd_dclkc1 [r/w] xxxxxxxx_xxxxxxxx osd_dclkc2 [r/w] xxxxxxxx_xxxxxxxx 0007802c h osd_dclkc3 [r/w] xxxxxxxx_xxxxxxxx osd_ioc1 [r/w] xxxxxxxx_xxxxxx00 00078030 h osd_ioc2 [r/w] xxxxxxxx_xxxxxxxx osd_dpc1 [r/w] xxxxxxxx_xxxxxxxx 00078034 h osd_dpc2 [r/w] xxxxxxxx_xxxxxxxx osd_dpc3 [r/w] xxxxxxxx_xxxxxxxx 00078038 h osd_dpc4 [r/w] xxxxxxxx_xxxxxxxx osd_irc [r/w] xxxxxxxx_xxxxxxxx 4 .com u datasheet
mb91310 series 36 (continued) *1 : the initial value of the register varies with the reset level. the initial value shown is the one after an init level reset. *2 : the initial value of the register varies with the reset level. the initial value shown is the one after an init level reset by the init pin. address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0007803c h osd_plt0 [r/w] xxxxxxxx_xxxxxxxx osd_plt1 [r/w] xxxxxxxx_xxxxxxxx osdc 00078040 h osd_plt2 [r/w] xxxxxxxx_xxxxxxxx osd_plt3 [r/w] xxxxxxxx_xxxxxxxx 00078044 h osd_plt4 [r/w] xxxxxxxx_xxxxxxxx osd_plt5 [r/w] xxxxxxxx_xxxxxxxx 00078048 h osd_plt6 [r/w] xxxxxxxx_xxxxxxxx osd_plt7 [r/w] xxxxxxxx_xxxxxxxx 0007804c h osd_plt8 [r/w] xxxxxxxx_xxxxxxxx osd_plt9 [r/w] xxxxxxxx_xxxxxxxx 00078050 h osd_plt10 [r/w] xxxxxxxx_xxxxxxxx osd_plt11 [r/w] xxxxxxxx_xxxxxxxx 00078054 h osd_plt12 [r/w] xxxxxxxx_xxxxxxxx osd_plt13 [r/w] xxxxxxxx_xxxxxxxx 00078058 h osd_plt14 [r/w] xxxxxxxx_xxxxxxxx osd_plt15 [r/w] xxxxxxxx_xxxxxxxx 0007805c h osd_act1 [r/w] xxxxxxxx_xxxxxxxx osd_act2 [r/w] xxxxxxxx_xxxxxxxx 00078060 h to 0007ffff h ? reserved 4 .com u datasheet
mb91310 series 37 n interrupt source, interrupt vector and interrupt register assignment (continued) interrupt source interrupt number interrupt level offset address of tbr default rn 10 16 reset 0 00 ? 3fc h 000ffffc h ? mode vector 1 01 ? 3f8 h 000ffff8 h ? system reserved 2 02 ? 3f4 h 000ffff4 h ? system reserved 3 03 ? 3f0 h 000ffff0 h ? system reserved 4 04 ? 3ec h 000fffec h ? system reserved 5 05 ? 3e8 h 000fffe8 h ? system reserved 6 06 ? 3e4 h 000fffe4 h ? coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h ? coprocessor error trap 8 08 ? 3dc h 000fffdc h ? inte instruction 9 09 ? 3d8 h 000fffd8 h ? instruction break exception 10 0a ? 3d4 h 000fffd4 h ? operand break trap 11 0b ? 3d0 h 000fffd0 h ? step trace trap 12 0c ? 3cc h 000fffcc h ? nmi request (tool) 13 0d ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? 3c4 h 000fffc4 h ? nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 3bc h 000fffbc h ? external interrupt 1 17 11 icr01 3b8 h 000fffb8 h ? external interrupt 2 18 12 icr02 3b4 h 000fffb4 h ? external interrupt 3 19 13 icr03 3b0 h 000fffb0 h ? external interrupt 4 (usb-function) 20 14 icr04 3ac h 000fffac h ? external interrupt 5 (usb-host) 21 15 icr05 3a8 h 000fffa8 h ? external interrupt 6 (osdc) 22 16 icr06 3a4 h 000fffa4 h ? external interrupt 7 23 17 icr07 3a0 h 000fffa0 h ? reload timer 0 24 18 icr08 39c h 000fff9c h 8 reload timer 1 25 19 icr09 398 h 000fff98 h 9 reload timer 2 26 1a icr10 394 h 000fff94 h 10 uart0(reception completed) 27 1b icr11 390 h 000fff90 h 0 uart1(reception completed) 28 1c icr12 38c h 000fff8c h 1 uart2(reception completed) 29 1d icr13 388 h 000fff88 h 2 uart0 (rx completed) 30 1e icr14 384 h 000fff84 h 3 uart1 (rx completed) 31 1f icr15 380 h 000fff80 h 4 uart2 (rx completed) 32 20 icr16 37c h 000fff7c h 5 4 .com u datasheet
mb91310 series 38 (continued) interrupt source interrupt number interrupt level offset address of tbr default rn 10 16 dmac0 (end, error) 33 21 icr17 378 h 000fff78 h ? dmac1 (end, error) 34 22 icr18 374 h 000fff74 h ? dmac2 (end, error) 35 23 icr19 370 h 000fff70 h ? dmac3 (end, error) 36 24 icr20 36c h 000fff6c h ? dmac4 (end, error) 37 25 icr21 368 h 000fff68 h ? a/d 38 26 icr22 364 h 000fff64 h ? ppg0 39 27 icr23 360 h 000fff60 h ? ppg1 40 28 icr24 35c h 000fff5c h ? ppg2 41 29 icr25 358 h 000fff58 h ? ppg3 42 2a icr26 354 h 000fff54 h ? pwc 43 2b icr27 350 h 000fff50 h ? system reserved 44 2c icr28 34c h 000fff4c h ? system reserved 45 2d icr29 348 h 000fff48 h ? main oscillation stabilization 46 2e icr30 344 h 000fff44 h ? timebase timer overflow 47 2f icr31 340 h 000fff40 h ? system reserved 48 30 icr32 33c h 000fff3c h ? clock timer 49 31 icr33 338 h 000fff38 h ? i 2 c ch0 50 32 icr34 334 h 000fff34 h ? i 2 c ch1 51 33 icr35 330 h 000fff30 h ? i 2 c ch2 52 34 icr36 32c h 000fff2c h ? i 2 c ch3 53 35 icr37 328 h 000fff28 h ? uart3(reception completed) 54 36 icr38 324 h 000fff24 h ? uart4(reception completed) 55 37 icr39 320 h 000fff20 h ? uart3 (rx completed) 56 38 icr40 31c h 000fff1c h ? uart4(reception completed) 57 39 icr41 318 h 000fff18 h ? timer0 58 3a icr42 314 h 000fff14 h ? timer1 59 3b icr43 310 h 000fff10 h ? timer2 60 3c icr44 30c h 000fff0c h ? timer3 61 3d icr45 308 h 000fff08 h ? system reserved 62 3e icr46 304 h 000fff04 h ? delay interrupt source bit 63 3f icr47 300 h 000fff00 h ? system reserved (used by realos) 64 40 ? 2fc h 000ffefc h ? system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h ? system reserved 66 42 ? 2f4 h 000ffef4 h ? 4 .com u datasheet
mb91310 series 39 (continued) interrupt source interrupt number interrupt level offset address of tbr default rn 10 16 system reserved 67 43 ? 2f0 h 000ffef0 h ? system reserved 68 44 ? 2ec h 000ffeec h ? system reserved 69 45 ? 2e8 h 000ffee8 h ? system reserved 70 46 ? 2e4 h 000ffee4 h ? system reserved 71 47 ? 2e0 h 000ffee0 h ? system reserved 72 48 ? 2dc h 000ffedc h ? system reserved 73 49 ? 2d8 h 000ffed8 h ? system reserved 74 4a ? 2d4 h 000ffed4 h ? system reserved 75 4b ? 2d0 h 000ffed0 h ? system reserved 76 4c ? 2cc h 000ffecc h ? system reserved 77 4d ? 2c8 h 000ffec8 h ? system reserved 78 4e ? 2c4 h 000ffec4 h ? system reserved 79 4f ? 2c0 h 000ffec0 h ? used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h ? 4 .com u datasheet
mb91310 series 40 n electrical characteristics 1. absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit remarks min max power supply voltage v dde (3.3 v) vss - 0.5 vss + 4.0 v v ddi (2.5 v) vss - 0.5 vss + 3.0 v analog power supply voltage av cc vss - 0.5 vss + 4.0 v input voltage v i vss - 0.5 vcc + 0.5 v analog pin input voltage v ia vss - 0.5 avcc + 0.5 v output voltage v o vss - 0.5 vcc + 0.5 v storage temperature tstg - 40 + 125 c parameter symbol value unit remarks min max operating temperature ta - 10 + 70 c power supply voltage v dde (3.3 v) 3.00 3.6 v v ddi (2.5 v) 2.30 2.70 analog power supply voltage av cc 3.00 3.60 v 4 .com u datasheet
mb91310 series 41 3. dc characteristics (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) *1 : p0 to p7, docki, hsync, ysync *2 : p0 to p7 *3 : b0 to b2, g0 to b2, r0 to r2, vob1, vob2, dck0, fh parameter sym- bol conditions value unit remarks min typ max power supply i cc rom product during normal operation ta = + 25 c, fcp = 40 mhz, fcpp = 20 mhz ? 200 250 ma MB91F312A dot clock@90 mhz 220 270 mb91fv310a dot clock@90 mhz i ccs main sleep mode ta = + 25 c, fcp = 40 mhz, fcpp = 20 mhz ? 150 180 ma MB91F312A dot clock pll stop 170 200 mb91fv310a dot clock pll stop i ccl sub run mode ta = + 25 c, fclk = 32 khz ? 800 1500 m a MB91F312A dot clock pll stop usb clock stop 1300 2000 mb91fv310a dot clock pll stop usb clock stop i cch main stop mode ta = + 25 c, fclk = 0 ? 70 150 m a MB91F312A 570 650 mb91fv310a ta = + 70 c, fclk = 0 ? 500 2000 m a MB91F312A 1000 2500 mb91fv310a i cct clock mode ta = + 25 c, fclk = 32 khz ? 600 1000 m a MB91F312A dot clock pll stop usb clock stop 1100 1500 mb91fv310a dot clock pll stop usb clock stop h level input voltage v ih *1 v cc 0.8 ? v cc v l level input voltage v il v cc = 3.3 v, *1 v ss ? v cc 0.2 v v cc = 2.5 v v cc 0.15 v h level output voltage v oh v dde = 3.3 v, i oh = - 4 ma, *2 v cc - 0.5 ? v cc v v dde = 2.5 v, i oh = - 4 ma, *3 v cc - 0.5 ? v cc v l level output voltage v ol v dde = 3.3 v, i ol = 4 ma, *2, *3 v ss ? 0.4 v input leak current i il ta = + 70 c - 5 ? +5 m a i 2 c bus switch connection resister rbs ??? 130 w between scl3 and scl4 between sda3 and sda4 4 .com u datasheet
mb91310 series 42 4. usb (1) dc characteristics (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) *1 : about the output short-circuit current i os the output short-circuit current ios is the maximum current that flows when the output pin is connected to vdde or vss (within the maximum rating). about the output short-circuit current: this is the short-circuit current per differential output pin on one side. as this usb i/o buffer is a differential output, consider both of the two pins. parameter sym- bol pin conditions value unit remarks min typ max h level output voltage v oh ? i oh = - 100 m av dde - 0.2 ? v dde v output level voltage v ol ? i ol = 100 m a0 ? 0.2 v h level output current i oh ? full speed v oh = v dde - 0.4 v - 20 ?? ma low speed v oh = v dde - 0.4 v - 6 ?? l level output current i ol ? full speed v ol = 0.4 v 20 ?? ma low speed v ol = 0.4 v 6 ?? output short circuit current i os ?? ?? 300 ma *1 input leak current i lz ?? ?? 5 m a*2 3-state enable "l" 3-state enable "l" monitor the short-circuit current short-circuited at gnd level monitor the short-circuit current short-circuited at v dde level h output l output h level l level 4 .com u datasheet
mb91310 series 43 *2 : about z leakage current i lz measurement the input leakage current i lz indicates the leakage current that flows when the v dde or v ss voltage is applied to the bidirectional pin with the usb i/o buffer in a high impedance state. 3-state enable "h" monitor the leakage current 0 v, v dd level applied to output pin z output 4 .com u datasheet
mb91310 series 44 (2) dc characteristics conforming to the usb specification revision 1.1. (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) *1 : about input voltages v ih and v il the single-end-receiver switching threshold voltage of the usb i/o buffer is set within the range of v il (max) = 0.8 v and v ih (min) = 2.0 v (ttl input standard). appropriate hysteresis is provided to reduce noise sensitivity. *2 : about input voltages v di and v cm the differential-receiver is used to receive usb differential data signals. the differential-receiver has a differential input sensitivity of 200 mv when the differential data input remains in the range of 0.8 to 2.5 v to the local ground reference level. the above voltage range is referred to as the common mode input voltage range. parameter symbol value unit remarks min max h level input voltage (driven) v ih 2.0 ? v*1 l level input voltage v il ? 0.8 v *1 diffential input sensitivity v di 0.2 ? v*2 differential common mode range v cm 0.8 2.5 v *2 h level output voltage (driven) v oh 2.8 3.6 v *3 l level output voltage v ol 0.0 0.3 v *3 external output signal crossover voltage v crs 1.3 2.0 v *4 bus pull-up resistor on upstream port rpu 1.425 1.575 k w 1.5 k w 5 % bus pull-down resistor on downstream port rpd 1.425 1.575 k w 1.5 k w 5 % termination voltage for upstream port pull-up v term 3.0 3.6 v *5 0.8 (v) 0.2 (v) 1.0 (v) 2.5 (v) minimum differential input sensitivity (v) common mode input voltage(v) 4 .com u datasheet
mb91310 series 45 *3 : about output voltages v ol and v oh the output drive capabilities of the driver are 0.3 v or less in low-state (v ol ) (when 1.5 k w is loaded at 3.6 v) and 2.8 v or more in high-state (v oh ) (when 15 k w is loaded at the ground). *4 : about output voltages v crs the cross voltage of the external differential output signal (d+/d-) of the usb i/o buffer ranges from 1.3 v to 2.0 v. *5 : about termination v term v term represents the pull-up voltage at the upstream port. d + max 2.0 (v) min 1.3 (v) d - v crs standard range 4 .com u datasheet
mb91310 series 46 5. ac characteristics (1) clock timing (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) (2) reset (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) * : init input time (at power-on) far, ceralock : f 2 15 or greater recommended crystal : f 2 21 or greater recommended f : power on ? x0/x1 period 2 parameter symbol pin condi- tions value unit remarks min typ max clock frequency fc x0, x1 ?? 10.135 ? mhz pll system (operation at a maximum internal speed of 40.54 mhz by quadrupling a self-oscillation frequency of 10.135 mhz via pll) internal operating clock frequency fcp ?? 2.53 ? 40.54 mhz cpu fcpp ?? 2.53 ? 20.27 mhz peripheral parameter symbol pin condi- tions value unit remarks min max init input time (at power-on) t intl init ? * ? ns init input time (other than at power - on) t cp 5 ? ns init input time (stop recovery time) * ? ns init t intl 0.2 v cc 4 .com u datasheet
mb91310 series 47 (3) uart timing (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) * : t cycp indicates the peripheral clock cycle time. note : ac characteristic in clk synchronized mode. parameter symbol pin conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck4 internal shift lock mode 8 t cycp * ? ns sck ? so delay time t slov sck0 to sck4 so0 to so4 - 80 + 80 ns valid si ? sck - t ivsh sck0 to sck4 si0 to si4 100 ? ns sck - ? valid si hold time t shix sck0 to sck4 si0 to si4 60 ? ns serial clock h pulse width t shsl sck0 to sck4 external shift lock mode 4 t cycp * ? ns serial clock l pulse width t slsh sck0 to sck4 4 t cycp * ? ns sck ? so delay time t slov sck0 to sck4 so0 to so4 ? 150 ns valid si ? sck - t ivsh sck0 to sck4 si0 to si4 60 ? ns sck - ? valid si hold time t shix sck0 to sck4 si0 to si4 60 ? ns 4 .com u datasheet
mb91310 series 48 internal shift clock mode external shift clock mode sck0 to sck4 t scyc t slov t ivsh t shix v ol v ol v oh v oh v ol v oh v ol v oh v ol so0 to so4 si0 to si4 t slsh t slov t ivsh t shix t shsl v oh v ol v oh v ol v oh v ol v oh v ol v ol v ol sck0 to sck4 so0 to so4 si0 to si4 4 .com u datasheet
mb91310 series 49 (4) reload timer clock, ppg timer input, and multi-function timer input timings (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) * : t cycp indicates the peripheral clock cycle time. (5) trigger input timing (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) * : t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit remarks min max input pulse width t tiwh t tiwl tin0 to tin2 ppg0 to ppg3 trg0 to trg3 ti0 to ti3 ? 2 t cycp * ? ns parameter symbol pin conditions value unit remarks min max a/d activation trigger input time t atrg atrg ? 5 t cycp * ? ns t tiwh t tiwl atrg t atrg 4 .com u datasheet
mb91310 series 50 (6) usb interface (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) *1 : the ac characteristics of the usb interface conform to the usb specification revision 1.1. *2 : about driver characteristics tr, tf, and tfrfm these represent the rise (tr) and fall (tf) time standards of the differential data signal. these are defined as times between 10% and 90% of the output signal voltage. for full-speed buffer, the tr/tf ratio is specified to fall within 10% to minimize rfi radiation. parameter symbol pin condi- tions value unit remarks min typ max input clock fucyc x0b, x1b ?? 48 * 1 ? mhz self-oscillation at a precision of 500 ppm * 1 x0b external input at a precision of 500 ppm * 1 rise time tr uhp/uhm udp/udm full speed 4 ? 20 ns *2 uhp/uhm low speed 75 ? 300 ns *2 fall time tf uhp/uhm udp/udm full speed 4 ? 20 ns *2 uhp/uhm low speed 75 ? 300 ns *2 differential rise and fall timing matching tfrfm uhp/uhm udp/udm full speed 90 ? 111.11 % *2 uhp/uhm low speed 80 ? 125 % *2 driver output resistance rzdrv udp udm ? 28 ? 44 w *3 x0b 10% 10% 90% 90% tf tr fucyc uhp udp uhm udm 4 .com u datasheet
mb91310 series 51 *3 : about driver characteristic zdrv usb full-speed connection is made by the twisted pair cable shielded at a characteristic impedance (z0) of 90 w 15%. the usb specification stipulates that the usb driver output impedance be within the range of 28 w to 44 w . the usb specification also stipulates that a discrete serial resistor (rs) be added for balancing purposes while satisfying the above standards. the output impedance of the usb i/o buffer in this lsi is about 3 w to 19 w . as the serial resistor rs, therefore, a 25 w to 30 w type (27 w type recommended) should be added. t d + t d - 3-state rs rs 28 w to 44 w equiv. imped. 28 w to 44 w equiv. imped. driver output impedance 3 w to 19 w rs 25 w to 30 w (recommended value: 27 w ) 4 .com u datasheet
mb91310 series 52 (7) analog rgb (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) parameter symbol pin conditions value unit remarks min typ max analog rgb output delay t vad rout, gout, bout v ref = 1.1 v, v ddr = v ddg = v ddb = 2.5 v, v ro = 2.7 k w , rcomp = gcomp = bcomp = 0.1 m f ? 5 ? ns ? analog rgb output settling time t vas rout, gout, bout ? 10 ? ns ? docki rout gout bout t vas t vad 1 lsb 1 lsb display signal output timing 4 .com u datasheet
mb91310 series 53 (8) digital rgb vertical sync, horizontal sync, and display output control signal input timings (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) *1 : during the horizontal sync signal pulse period, the device stops its internal osdc operation, disabling writing to the internal vram. therefore, set the horizontal sync signal pulse width and vram write cycle to ensure that: horizontal sync signal pulse width < vram write cycle. precisely, adjust the command issuance interval not to issue command 2 or command 4 (vram write command) more than once in the horizontal sync signal pulse with period. if the above condition is not satisfied, the device may fail writing to vram. *2 : 1h is assumed to be one horizontal sync signal period. parameter symbol pin value unit remarks min max horizontal sync signal cycle time t hcyc hsync 100 + t wh ? dot clock horizontal sync signal pulse width t wh hsync 20 ? dot clock *1 ? 6 m s horizontal sync signal setup time t dhst hsync 4 ? ns horizontal sync signal hold time t dhhd 0 ? ns vertical sync signal setup time t hvst vsync 51h* 2 - 5dot clock vertical sync signal hold time t hvhd 3 ? h* 2 input sync signal rise/fall time t dr t df hsync vsync ? 5ns docki hsync 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t dhst t dhhd t dr , t df horizontal sync, and display output control signal input timings 4 .com u datasheet
mb91310 series 54 hsync 0.8 v dd 0.2 v dd 0.8 v dd 0.8 v dd 0.2 v dd t hcyc t wh t dr t df 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t hvhd t hvst t dr t df hsync vsync 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t wh t dr t df 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t hvhd t hvst t dr t df hsync vsync 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t wh t dr t df horizontal sync signal input vertical sync signal input timing leading edge of hsync trailing edge of hsync 4 .com u datasheet
mb91310 series 55 display signal timing (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = 0 v) *1 : input a continuous dot clock signal without a break. *2 : output load of 16 pf parameter symbol pin value unit remarks min max dot clock input cycle time t dif docki 11 90 mhz *1 dot clock input pulse width t diwh docki 3.5 ? ns *1 t diwl 3.5 ? ns dot clock output delay time 1 t pdc dcko 3 8 ns *2 display signal output delay time i1 t pdi1 r2 to r0, b2 to b0, g2 to g0, vob1, vob2 28ns*2 display signal output delay time o1 t pdo1 r2 to r0, b2 to b0, g2 to g0, vob1, vob2 - 45ns*2 docki dcko r2 to r0 g2 to g0 b2 to b0 vob1, vob2 t dif t pdi1 t pdo1 t pdc t pdc 0.8 v dd 0.8 v dd 0.2 v dd 0.2 v dd 0.8 v dd 0.2 v dd 0.8 v dd 0.5 v dd t diwh t diwl display signal output timing 4 .com u datasheet
mb91310 series 56 6. 0.25 m m m m m technology about the power-on sequence for dual-power-supply models ? the power supplies must be turned on in the vddi ? avcc, avrh ? vdde order and off in the vdde ? avcc, avrh ? vddi order. when vddi is turned on earlier, the potential difference between vddi and vdde must be within 3.6 v. ? turn on vdde before turning on analog power supply avcc and applying the analog signal. 7. electrical characteristics for the a/d converter (ta = - 10 c to + 70 c, v dde = 3.3 v 0.3 v, v ddi = 2.5 v 0.2 v, vss = av ss = 0 v, av rh = 3.0 v to 3.6 v) *1 : measured in the cpu sleep state *2 : depends on the clock cycle of the clock signal supplied to peripheral resources. parameter value unit remarks min typ max resolution ?? 10 bit total error* 1 - 5.5 ? + 5.5 lsb avcc = 3.3 v, av rh = 3.3 v (cpu in sleep mode) nonlinear error* 1 - 3.5 ? + 3.5 lsb differential linear error* 1 - 2.0 ? + 2.0 lsb zero transition voltage* 1 - 4.0 ? + 6.0 lsb full transition voltage* 1 av rh - 5.5 ? av rh + 3.0 lsb conversion time 10 *2 ??m s power supply current (analog + digital) ? 3.6 ? ma ?? 5 m a stop converting reference power supply current (between avrh and avrl) ? 470 ?m aav rh = 3.0 v, av rl = 0.0 v ?? 10 m a stop converting analog input capacitance ? 40 ? pf interchannel disparity ?? 4lsb r on1 r on2 c 0 c 1 an0 to an9 analog input pin comparator r on1 = approx. 300 w r on2 = approx. 60 w c 0 = approx. 40 pf c 1 = approx. 4 pf 4 .com u datasheet
mb91310 series 57 n ordering information part number package remarks MB91F312Apfv-1xx-bnd-e1 144-pin plastic lqfp (fpt-144p-m08) lead free package mb91fv310apfv-es 144-pin plastic lqfp (fpt-144p-m08) for development tools 4 .com u datasheet
mb91310 series 58 n package dimension 144-pin plastic lqfp (fpt-144p-m08) note 1) * : values do not include resin protrusion. resin protrusion is + 0.25 (.010) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f144019s-c-4-6 details of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 C0.10 +.008 C.004 .059 0 ? ~8 ? 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 20.000.10(.787.004)sq 22.000.20(.866.008)sq (mounting height) * 4 .com u datasheet
mb91310 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0311 ? fujitsu limited printed in japan 4 .com u datasheet

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